With recent advances in the development of high density very large scale integration (VLSI) circuits, the dimensions of the devices continue to shrink resulting in a corresponding decrease in the gate oxide thicknesses in the CMOS devices. This decrease, relative to breakdown voltage, has resulted in the greater susceptibility of these devices to damage from the application of excessive voltages such as caused by an electrostatic discharge (ESD) event. During an ESD event, charge is transferred between one or more pins of the integrated circuits and another conducting object in a short period of time, typically less than one microsecond. The charge transfer generates voltages that are large enough to break down insulating films, e.g., gate oxides on MOSFET devices, or that can dissipate sufficient energy to cause electrothermal failures in the devices. Such failures include contact spiking, silicon melting, or metal interconnect melting. Consequently, in order to deal with transient ESD pulses, an integrated circuit must incorporate protection circuits at every input and I/O pin. Various circuit structures for ESD protection can be found, e.g., in U.S. Pat. Nos. 5,019,888 to Scott et al; 5,182,220 to Ker et al; 5,218,222 to Roberts; and 5,329,143 to Chan; and in the literature in "Internal Chip ESD Phenomena Beyond the Protection Circuit", C. Duvvury, IEEE Transactions on Electron Devices, Vol.35, No.12, Dec. 1988; "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", A. Chatterjee, IEEE Electron Device Letters, Vol.12, No.1, Jan. 1991; and "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50 - and 0.25-.mu.m Channel Length CMOS Technologies", S. Voldman, EOS/ESD Symposium Proceedings, pp. 125-134, 1994.
An example of an integrated circuit having such protection is shown in FIG. 1, which is a cross-sectional view of a conventional integrated circuit (IC) device 10 fabricated from a semiconductor substrate 12 of a first conductivity type, such as P-type conductivity, with various diffusions and circuit components formed thereon including those for protecting against ESD damage due to excessive stresses occurring between applied voltages Vss and Vcc and the voltage on an I/O Pad 15. Specifically, on the left side of the Pad, is a thin-oxide NMOS field-effect transistor (MOSFET) 26, composed of N+ regions, 18 and 20, and a gate electrode 22, with a thin oxide 24 therebetween, and having its outer N+ region 18 coupled to an adjacent outer P+ conductivity region 14, which is connected by a contact or bus 16 to a negative voltage source Vss. The inner N+ region 20 is also coupled to an adjacent P+ conductivity region 14 connected to negative voltage source Vss, This NMOS thick-field device 26 deals with either positive or negative ESD stresses developed between the Vss voltage on contact 16 and the voltage communicated from the Pad 15 to a Pad-connected contact 28 on inner N+ region 20. As illustrated in the Figure, the N+ diffusion regions, 18 and 20, and underlying P-type substrate 12 act as a bipolar device T1 when there is an excessive positive stress on the Pad contact 28 with respect to Vss, i.e., a parasitic lateral NPN transistor results, with its base at the substrate 12, its emitter at N+ area 18, and its collector at N+ area 20, which breaks down to offer protection to the other circuit devices. Specifically, junction breakdown occurs, typically at about 13 volts for a CMOS device, and the generated electrons are swept into the collector region 20. The generated holes injected into the base region 12 cause the substrate voltage to increase, forward biasing the emitter junction, and causing the transistor T1 to turn ON. As a consequence, injection of electrons from the emitter 18 into the base 12 is increased and those electrons reaching the collector base junction generate new electron hole pairs and current growth continues. This "positive feedback" causes the emitter-to-collector current to increase indefinitely resulting in damage to the device if the current is not somehow limited. When a negative stress on the Pad contact 28 with respect to Vss occurs, a forward biased diode Dl results between P+ region 14 and N+ region 20, through the substrate 12, that will turn ON to protect the other integrated devices.
On the other side of the Pad contact 28, and coupled thereto is a P-channel device comprised of an N-well 30 in the substrate 12 containing P+ regions 32 and 34 which have a gate electrode 36 disposed above and extending between them with a thin oxide 38 therebetween so as to form a thin-oxide PMOS field-effect transistor (MOSFET) 40. A contact or bus 42, coupled to an operating voltage source Vcc, connects outer P+ region 34 to an outer N+ region 44 also within the N-well 30. The inner P+ region 32 is coupled to Pad contact 28 and has an adjacent N+ conductivity region 44 connected to operating voltage source Vcc, with both regions 32 and 44 also within the N-well 30. The PMOS device 40 deals with either positive or negative ESD stresses developed between the Vcc voltage on contact 42 and the voltage on the Pad-connected contact 28. When an ESD stress is set up with respect to Vcc and contact 28, diodes D2 result between the P+ region 32 and the N+ regions 44, through the N-well 30. In particular, when there is an excessive positive stress on the Pad contact 28 with respect to Vcc, diodes D2 will turn ON, while when this ESD stress event is negative diodes D2 will suffer avalanche-breakdown. It will thus be seen that such a prior art construction while offering a degree of protection from ESD events still may suffer breakdown and damage.
It is therefore an object of the present invention to provide an enhanced ESD protection performance apparatus and method to protect VLSI circuits and particularly CMOS devices.
It is another object of the present invention to provide an enhanced ESD protection performance apparatus and method to protect VLSI circuits and particularly CMOS devices utilizing the addition of at least one capacitance in the line between the Vcc and Vss sources.